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(R)
TDA7449L
LOW COST DIGITALLY CONTROLLED AUDIO PROCESSOR
INPUT MULTIPLEXER - 2 STEREO INPUTS - SELECTABLE INPUT GAIN FOR OPTIMAL ADAPTATION TO DIFFERENT SOURCES ONE STEREO OUTPUT VOLUME CONTROL IN 1.0dB STEPS TWO SPEAKER ATTENUATORS: - TWO INDEPENDENT SPEAKER CONTROL IN 1.0dB STEPS FOR BALANCE FACILITY - INDEPENDENT MUTE FUNCTION ALL FUNCTION ARE PROGRAMMABLE VIA SERIAL BUS DESCRIPTION The TDA7449L is a volume control and balance (Left/Right) processor for quality audio applications in TV systems. Selectable input gain is provided. Control of all the functions is accomplished by serial bus. The AC signal setting is obtained by resistor netBLOCK DIAGRAM
MUXOUTL 8 100K 9 100K G VOLUME 10
DIP20
ORDERING NUMBER: TDA7449L
works and switches combined with operational amplifiers. Thanks to the used BIPOLAR/CMOS Technology, Low Distortion, Low Noise and DC stepping are obtained.
L-IN1
L-IN2
SPKR ATT LEFT
5 LOUT
19 R-IN1 7 100K 6 G 100K VOLUME SPKR ATT RIGHT VREF 2 INPUT MULTIPLEXER + GAIN 11 MUXOUTR SUPPLY 3 0/30dB 2dB STEP I CBUS DECODER + LATCHES
2
20 18
SCL SDA DIG_GND
R-IN2
4
ROUT
VS AGND
1 CREF
D98AU868
April 1999
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TDA7449L
ABSOLUTE MAXIMUM RATINGS
Symbol VS Tamb Tstg Operating Supply Voltage Operating Ambient Temperature Storage Temperature Range Parameter Value 10.5 -10 to 85 -55 to 150 Unit V C C
PIN CONNECTION
CREF VS PGND ROUT LOUT R_IN2 R_IN1 L_IN1 L_IN2 MUXOUT(L)
1 2 3 4 5 6 7 8 9 10
D98AU869
20 19 18 17 16 15 14 13 12 11
SDA SCL DIG_GND N.C. N.C. N.C. N.C. N.C. N.C. MUXOUT(R)
THERMAL DATA
Symbol R th j-pin Parameter Thermal Resistance Junction-pins Value 150 Unit C/W
QUICK REFERENCE DATA
Symbol VS VCL THD S/N SC Supply Voltage Max. input signal handling Total Harmonic Distortion V = 1Vrms f = 1KHz Signal to Noise Ratio V out = 1Vrms (mode = OFF) Channel Separation f = 1KHz Input Gain in (2dB step) Volume Control Balance Control Mute Attenuation (1dB step) 1dB step 0 -47 -79 100 Parameter Min. 6 2 0.01 106 90 30 0 0 0.1 Typ. 9 Max. 10.2 Unit V Vrms % dB dB dB dB dB dB
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TDA7449L
ELECTRICAL CHARACTERISTICS (refer to the test circuit Tamb = 25C, VS = 9V, RL= 10K, RG = 600, all controls flat (G = 0dB), unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit
SUPPLY
VS IS SVR Supply Voltage Supply Current Ripple Rejection 6 60 9 7 90 10.2 V mA dB
INPUT STAGE
R IN V CL SIN Ginmin Ginman Gstep Input Resistance Clipping Level Input Separation Minimum Input Gain Maximum Input Gain Step Resolution THD = 0.3% The selected input is grounded through a 2.2 capacitor 2 80 -1 100 2.5 100 0 30 2 1 K Vrms dB dB dB dB
VOLUME CONTROL
C RANGE AVMAX ASTEP EA ET VDC Amute Control Range Max. Attenuation Step Resolution Attenuation Set Error Tracking Error DC Step Mute Attenuation AV = 0 to -24dB AV = -24 to -47dB AV = 0 to -24dB AV = -24 to -47dB adjacent attenuation steps from 0dB to AV max 80 45 45 0.5 -1.0 -1.5 47 47 1 0 0 0 0 0 0.5 100 49 49 1.5 1.0 1.5 1 2 3 dB dB dB dB dB dB dB mV mV dB
SPEAKER ATTENUATORS
C RANGE SSTEP EA VDC Amute VCLIP RL RO VDC Control Range Step Resolution Attenuation Set Error DC Step Mute Attenuation AV = 0 to -20dB AV = -20 to -56dB adjacent attenuation steps 0.5 -1.5 -2 80 76 1 0 0 0 100 1.5 1.5 2 3 dB dB dB dB mV dB
AUDIO OUTPUTS
Clipping Level Output Load Resistance Output Impedance DC Voltage Level d = 0.3% 2.1 2 10 2.6 40 3.8 70 VRMS K V V dB dB dB dB %
GENERAL
ENO Et S/N SC d Output Noise Total Tracking Error Signal to Noise Ratio Channel Separation Left/Right Distortion All gains = 0dB; BW = 20Hz to 20KHz flat AV = 0 to -24dB AV = -24 to -47dB All gains 0dB; VO = 1VRMS ; 80 AV = 0; VI = 1VRMS ; 5 0 0 106 100 0.01 15 1 2
0.08
BUS PUT
IN3/13
TDA7449L
ELECTRICAL CHARACTERISTICS (continued.)
Symbol Parameter Test Condition Min. Typ. Max. Unit
BUS INPUT
V IL VIH IIN VO Input Low Voltage Input High Voltage Input Current Output Voltage SDA Acknowledge 1 VIN = 0.4V IO = 1.6mA 3 -5 0.4 5 0.8 V V A V
TEST CIRCUIT
MUXOUTL 10 L-IN1 0.47F 8 100K
L-IN2 0.47F
9 100K G VOLUME SPKR ATT LEFT
5
LOUT
R-IN1 0.47F
7 100K
0/30dB 2dB STEP
19 I CBUS DECODER + LATCHES
2
20 18
SCL SDA DIG_GND
R-IN2 0.47F
6 100K G VOLUME SPKR ATT RIGHT VREF
4
ROUT
2 INPUT MULTIPLEXER + GAIN 11 MUXOUTR SUPPLY 3
VS AGND
1 CREF 10F
D98AU870
APPLICATION SUGGESTIONS The first and the last stages are volume control blocks. The control range is 0 to -47dB (mute) for the first one, 0 to -79dB (mute) for the last one. Both of them have 1dB step resolution. The very high resolution allows the implementation of systems free from any noisy acoustical effect.
The TDA7449L audioprocessor provides 2 bands tones control. CREF The suggested 10F reference capacitor (CREF) value can be reduced to 4.7F if the application requires faster power ON.
4/13
TDA7449L
Figure 2: THD vs. frequency Figure 3: THD vs. RLOAD
Figure 4: Channel separation vs. frequency
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TDA7449L
I2C BUS INTERFACE Data transmission from microprocessor to the TDA7449L and vice versa takes place through the 2 wires I 2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). Data Validity As shown in fig. 3, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown in fig.4 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acFigure 3: Data Validity on the I2CBUS knowledge bit. The MSB is transferred first. Acknowledge The master (P) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 5). The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during this clock pulse. The audio processor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. Transmission without Acknowledge Avoiding to detect the acknowledge of the audio processor, the P can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking.
Figure 4: Timing Diagram of I2CBUS
Figure 5: Acknowledge on the I2CBUS
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TDA7449L
SOFTWARE SPECIFICATION Interface Protocol The interface protocol comprises: A start condition (S) A chip address byte, containing the TDA7449L address A subaddress bytes A sequence of data (N byte + acknowledge) A stop condition (P)
CHIP ADDRESS MSB S 1 0 0 0 1 0 0 LSB 0 ACK MSB X X
SUBADDRESS LSB X B DATA ACK MSB
DATA 1 to DATA n LSB DATA ACK P
D96AU420
ACK = Acknowledge S = Start P = Stop A = Address B = Auto Increment
EXAMPLES No Incremental Bus The TDA7449L receives a start condition, the cor-
rect chip address, a subaddress with the B = 0 (no incremental bus), N-data (all these data concern the subaddress selected), a stop condition.
CHIP ADDRESS MSB S 1 0 0 0 1 0 0 LSB 0 ACK MSB X X
SUBADDRESS LSB X 0 D3 D2 D1 D0 ACK MSB
DATA LSB DATA ACK P
D96AU421
Incremental Bus The TDA7449L receive a start conditions, the correct chip address, a subaddress with the B = 1 (incremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas
SUBADDRESS from "XXX1000" to "XXX1111" of DATA are ignored. The DATA 1 concern the subaddress sent, and the DATA 2 concern the subaddress sent plus one in the loop etc, and at the end it receivers the stop condition.
CHIP ADDRESS MSB S 1 0 0 0 1 0 0 LSB 0 ACK MSB X X
SUBADDRESS LSB X 1 D3 D2 D1 D0 ACK MSB
DATA 1 to DATA n LSB DATA ACK P
D96AU422
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TDA7449L
POWER ON RESET CONDITION
INPUT SELECTION INPUT GAIN VOLUME SPEAKER IN2 28dB MUTE MUTE
DATA BYTES Address = 88 HEX (ADDR:OPEN). FUNCTION SELECTION: First byte (subaddress)
MSB D7 X X X X X X X X D6 X X X X X X X X D5 X X X X X X X X D4 B B B B B B B B D3 0 0 0 0 0 0 0 0 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 SUBADDRESS INPUT SELECT INPUT GAIN VOLUME NOT USED NOT USED NOT USED SPEAKER ATTENUATE "R" SPEAKER ATTENUATE "L"
B = 1: INCREMENTAL BUS ACTIVE B = 0: NO INCREMENTAL BUS X = DON'T CARE
In Incremental Bus Mode, the three "not used" functions must be addressed in any case. For example to refresh "Volume = 0dB" and Speaker_R = -40dB", the following bytes must be sent:
SUBADDRESS VOLUME DATA NOT USED 1 DATA NOT USED 2 DATA NOT USED 3 DATA SPEAKER_R DATA XXX10010 X0000000 XXXX1111 XXXX1111 XXXX1111 X0000010
INPUT SELECTION
MSB D7 X X X X D6 X X X X D5 X X X X D4 X X X X D3 X X X X D2 X X X X D1 0 0 1 1 LSB D0 0 1 0 1 INPUT MULTIPLEXER NOT ALLOWED NOT ALLOWED IN2 IN1
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TDA7449L
DATA BYTES (continued) INPUT GAIN SELECTION
MSB D7 D6 D5 D4 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
GAIN = 0 to 30dB
LSB D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
INPUT GAIN 2dB STEPS 0dB 2dB 4dB 6dB 8dB 10dB 12dB 14dB 16dB 18dB 20dB 22dB 24dB 26dB 28dB 30dB
VOLUME SELECTION
MSB D7 D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 0 0 0 0 0 0 X
VOLUME = 0 to 47dB/MUTE
LSB D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1
VOLUME 1dB STEPS 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB 0dB -8dB -16dB -24dB -32dB -40dB
0 0 0 0 1 1 1
0 0 1 1 0 0 1
0 1 0 1 0 1 1 X X X
MUTE
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TDA7449L
DATA BYTES (continued) SPEAKER ATTENUATE SELECTION
MSB D7 D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 1 X X X D1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 SPEAKER ATTENUATION 1dB 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB 0dB -8dB -16dB -24dB -32dB -40dB -48dB -56dB -64dB -72dB MUTE
SPEAKER ATTENUATION = 0 to -79dB/MUTE
PIN: 1
PINS: 4, 5
VS
VS
VS 20K
ROUT LOUT 24
CREF 20K
20A
D96AU430
D96AU434
10/13
TDA7449L
PINS: 6,7,8,9 PINS: 10,11
VS 20A
MUXOUT
VS
VS 20A
IN
100K
GND
VREF
D96AU425
D96AU491
PIN: 19
PIN: 20
20A SCL
SDA
20A
D96AU423
D96AU424
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TDA7449L
mm MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.34 8.5 2.54 22.86 7.1 3.93 0.130 0.053 0.254 1.39 0.45 0.25 25.4 0.335 0.100 0.900 0.280 0.155 1.65 TYP. MAX. MIN. 0.010 0.055 0.018 0.010 1.000 0.065 inch TYP. MAX.
DIM.
OUTLINE AND MECHANICAL DATA
DIP20
12/13
TDA7449L
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com
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